Advances in integrated circuit manufacturing technologies make possible electronic systems comprising tens or even hundreds of millions of active devices. These improvements provide for increased numbers of interconnection layers supporting advanced clocking schemes, more signal wiring, and more complex control schemes. The market demand for such systems has led to increased system performance, decreased device size, and greater feature sets. These system and technology improvements drive ever-increasing design complexity. Increased design complexity, in turn, creates engineering challenges regarding circuit design, system architecture, signal distribution and control, and chip fabrication. This design complexity has necessitated greater scrutiny of system architectures, logic circuits, interconnection schemes, and control and data distribution methods. As a result, new architectures, technologies, and circuit families have been developed to take advantage of total device count and smaller device sizes. Simplified wiring and control schemes have appeared as well. The various possible system architectures provide certain benefits and costs which require careful design consideration.
The operation of highly complex and dense integrated circuits (chips) is typically orchestrated by a system clock signal. The clock signal may take many forms—including multiple phases—but in all of its forms the clock signal is used to synchronize operations across the entire chip, ensuring that all portions of the chip work together properly. Further, as a result of the ubiquitous nature of the clock signal, this signal must be distributed to virtually every circuit across the entire chip. Thus, the difference in arrival time (skew) of the clock signal across the entire chip must be kept to a minimum.
The most efficient method for delivering a clock signal with the lowest skew across an entire chip is to use the chip interconnect with the lowest resistance and thus implement a metal distribution grid. Many grid patterns have been proposed, with some integrated circuit architects dedicating entire metallization layers solely to the distribution of the clock signal. Each proposed grid pattern has its relative advantages and disadvantages dictated by factors such as design complexity, metallization utilization (density), and power dissipation. One common clock distribution network is based on a recursive H Tree. The H Tree resembles the letter H, and is derived from a family of fractal sets. In addition to this wiring pattern, various circuits, including clock retimers, buffers, and amplifiers, must be added to the many clock signal distribution lines in order to minimize propagation time and thus also minimize clock signal skew. For each clock cycle, the clock distribution tree and commensurate retimers, buffers, and amplifiers must be loaded and unloaded, thus increasing power dissipation and reducing maximum clock rate.